CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 2211/5621 (2013.01); G11C 2211/5622 (2013.01)] | 20 Claims |
1. A memory device, comprising:
a cell array comprising non-volatile memory cells, each non-volatile memory cell capable of storing multi-bit data corresponding to a plurality of program states and an erased state; and
a control circuit configured to perform at least two partial program operations for programming the multi-bit data to at least two non-volatile memory cells,
wherein the at least two partial program operations include:
an Incremental Step Pulse Programming (ISPP) operation to increase threshold voltages of the at least two non-volatile memory cells from the erased state to a first program state among the plurality of program states, and
a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.
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