US 11,990,191 B2
Apparatus and method for programming data in a non-volatile memory device
Hyung Jin Choi, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Feb. 16, 2022, as Appl. No. 17/673,308.
Claims priority of application No. 10-2021-0131551 (KR), filed on Oct. 5, 2021.
Prior Publication US 2023/0104044 A1, Apr. 6, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 7/10 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 7/1039 (2013.01); G11C 11/5628 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/3404 (2013.01); G11C 2211/5621 (2013.01); G11C 2211/5622 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a cell array comprising non-volatile memory cells, each non-volatile memory cell capable of storing multi-bit data corresponding to a plurality of program states and an erased state; and
a control circuit configured to perform at least two partial program operations for programming the multi-bit data to at least two non-volatile memory cells,
wherein the at least two partial program operations include:
an Incremental Step Pulse Programming (ISPP) operation to increase threshold voltages of the at least two non-volatile memory cells from the erased state to a first program state among the plurality of program states, and
a single pulse program operation to increase a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state which is higher than the first program state among the plural program states.