US 11,990,190 B2
Memory device to execute read operation using read target voltage
Hiroshi Maejima, Tokyo (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 9, 2023, as Appl. No. 18/332,472.
Application 18/332,472 is a continuation of application No. 17/377,857, filed on Jul. 16, 2021, granted, now 11,715,533.
Application 17/377,857 is a continuation of application No. 16/891,407, filed on Jun. 3, 2020, granted, now 11,101,005, issued on Aug. 24, 2021.
Application 16/891,407 is a continuation of application No. 16/210,537, filed on Dec. 5, 2018, granted, now 10,699,792, issued on Jun. 30, 2020.
Application 16/210,537 is a continuation of application No. 15/902,399, filed on Feb. 22, 2018, granted, now 10,186,323, issued on Jan. 22, 2019.
Application 15/902,399 is a continuation of application No. 15/445,985, filed on Mar. 1, 2017, granted, now 9,922,717, issued on Mar. 20, 2018.
Claims priority of application No. 2016-181534 (JP), filed on Sep. 16, 2016.
Prior Publication US 2023/0352105 A1, Nov. 2, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01); G11C 16/3459 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A memory device comprising:
a semiconductor substrate having a main surface extending in a first direction and a second direction crossing the first direction;
a bit line provided on a side of the main surface in a third direction that crosses the first direction and the second direction and extending the first direction;
a first semiconductor pillar electrically connected to the bit line and extending in the third direction, the first semiconductor pillar having a first joint portion at a position in the third direction;
a second semiconductor pillar electrically connected to the bit line and extending in the third direction, the second semiconductor pillar having a second joint portion at the same position with the first joint portion in the third direction;
a first conductive member extending in the second direction and intersecting the first semiconductor pillar, the first conductive member being provided between the first joint portion and the bit line;
a second conductive member extending in the second direction and intersecting the second semiconductor pillar, the first and second conductive members being at a same position in the third direction, the second conductive member being electrically disconnected from the first conductive member;
a third conductive member extending in the second direction and intersecting the first semiconductor pillar, the third conductive member being provided between the first joint portion and the semiconductor substrate in the third direction;
a fourth conductive member extending in the second direction and intersecting the second semiconductor pillar, the third and fourth conductive members being at a same position in the third direction, the fourth conductive member being electrically disconnected from the third conductive member;
a fifth conductive member extending in the second direction and intersecting the first semiconductor pillar, the fifth conductive member being provided between the first conductive member and the bit line;
a sixth conductive member extending in the second direction and intersecting the second semiconductor pillar, the fifth and sixth conductive members being at a same position in the third direction, the sixth conductive member being electrically connected to the fifth conductive member;
a seventh conductive member extending in the second direction and intersecting the first semiconductor pillar, the seventh conductive member being provided between the substrate and the first joint portion; and
an eighth conductive member extending in the second direction and intersecting the second semiconductor pillar, the seventh and eighth conductive members being at a same position in the third direction, the eighth conductive member being electrically connected to the seventh conductive member.