CPC G11C 16/3427 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
1. A nonvolatile memory device comprising:
at least one memory block including a plurality of cell strings where each of the plurality of cell strings includes a string selection transistor, a plurality of memory cells and a ground selection transistor which are connected in series and disposed in a vertical direction between a source line and a bit-line, the plurality of cell strings being divided into a plurality of stacks disposed in the vertical direction, each of the plurality of stacks including at least one dummy word-line adjacent to a boundary between the plurality of stacks; and
a control circuit configured to control a program operation by:
applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period; and
reducing a voltage level of a dummy voltage applied to the at least one dummy word-line of at least one upper stack from among the plurality of stacks during the program execution period, wherein:
the at least one upper stack is disposed at a higher position than a selected stack in the vertical direction, and
the selected stack from among the plurality of stacks includes the selected word-line.
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