| CPC G11C 16/26 (2013.01) [G06F 11/1068 (2013.01); G11C 16/0483 (2013.01)] | 15 Claims |
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8. A semiconductor apparatus, comprising:
a first array readout component, adapted to read data from a NAND first memory cell array;
a second array readout component, adapted to read data from a NAND second memory cell array;
a first holding component, adapted to hold the data read by the first array readout component;
a second holding component, adapted to hold the data read by the second array readout component;
an output component, adapted to output the data held by the first holding component and the second holding component in synchronization with a clock signal; and
a control component, adapted to control a readout action,
wherein, providing that the control component controls continuous readout of pages, the first array readout component reads a first data of a half page, the second array readout component reads a second data of a half page, and the output component outputs the first data and the second data alternately and continuously,
wherein the first holding component comprises: a first latch, adapted to hold the first data read by the first array readout component; and a second latch, adapted to hold the first data transferred from the first latch, wherein after the first data is transferred from the first latch to the second latch, a first data of a half page of a next page read by the first array readout component is held in the first latch; and
the second holding component comprises: a first latch, adapted to hold the second data read by the second array readout component; and a second latch, adapted to hold the second data transferred from the first latch, wherein after the second data is transferred from the first latch to the second latch, a second data of a half page of a next page read by the second array readout component is held in the first latch.
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