US 11,990,187 B2
Method and apparatus with memory array programming
Seok Ju Yun, Hwaseong-si (KR); Daekun Yoon, Suwon-si (KR); Sang Joon Kim, Hwaseong-si (KR); and Seungchul Jung, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Aug. 4, 2022, as Appl. No. 17/880,849.
Claims priority of application No. 10-2021-0167091 (KR), filed on Nov. 29, 2021.
Prior Publication US 2023/0170026 A1, Jun. 1, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/20 (2006.01); G11C 16/32 (2006.01); G11C 29/52 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 11/5628 (2013.01); G11C 16/10 (2013.01); G11C 16/20 (2013.01); G11C 16/32 (2013.01); G11C 16/3418 (2013.01); G11C 16/3427 (2013.01); G11C 29/52 (2013.01); G11C 2211/5621 (2013.01)] 36 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array comprising memory cells; and
a memory controller configured to control programming of the memory cells of the memory array;
wherein the memory controller is configured to:
repeat for a plurality of times:
a generation of a first present time current error between a first present time current and a first target current, both of a first memory cell;
a generation of a second present time current error between a second present time current and a second target current, both of a second memory cell, where a greatest among the first present time current error and the second present time current error is a greatest present time current error; and
a programming of a select one of the first and second memory cells that has the greatest present time current error.