US 11,990,186 B2
One-ladder read of memory cells coarsely programmed via interleaved two-pass data programming techniques
Phong Sy Nguyen, Livermore, CA (US); James Fitzpatrick, Laguna Niguel, CA (US); and Kishore Kumar Muchherla, Fremont, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Apr. 20, 2022, as Appl. No. 17/724,940.
Application 17/724,940 is a continuation of application No. 17/127,502, filed on Dec. 18, 2020, granted, now 11,335,407.
Prior Publication US 2022/0246214 A1, Aug. 4, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/10 (2006.01); G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/10 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0644 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 11/56 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device, comprising:
memory cells; and
a logic circuit coupled with the memory cells and configured to:
receive a plurality of pages of data bits; and
program a page of the memory cells to have threshold voltages representative of the plurality of pages of data bits, via:
programming, in a first pass, a threshold voltage of each respective memory cell in the page of the memory cells to a respective first level representative of a combination of bit values, each of the bit values being from one of the plurality of pages of data bits;
computing a group identification for the respective memory cell; and
increasing a voltage applied to the page of the memory cells to a sequence of read voltages in an increasing order to retrieve the plurality of pages of data bits from the page of the memory cells.