CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/0061 (2013.01)] | 20 Claims |
1. An operation method of a memory device, wherein the memory device comprises a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector, and the operation method comprises:
providing a voltage pulse to the memory device in an operation cycle, wherein a voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector, a critical voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is from 100 MV/s to 10 GV/s, and the falling part of the voltage pulse declines by multiple steps; and
repeating the operation cycle, wherein a threshold voltage drift of the two-terminal selector during the operation cycles is less than 0.5 V.
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