US 11,990,182 B2
Operation methods for ovonic threshold selector, memory device and memory array
Hengyuan Lee, Hsinchu (TW); Cheng-Hsien Wu, Hsinchu (TW); Yu-Sheng Chen, Taoyuan (TW); Elia Ambrosi, Hsinchu (TW); Chien-Min Lee, Hsinchu County (TW); and Xinyu Bao, Fremont, CA (US)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 18, 2022, as Appl. No. 17/577,409.
Claims priority of provisional application 63/214,777, filed on Jun. 24, 2021.
Prior Publication US 2022/0415391 A1, Dec. 29, 2022
Int. Cl. G11C 13/00 (2006.01)
CPC G11C 13/004 (2013.01) [G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 13/0038 (2013.01); G11C 13/0061 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An operation method of a memory device, wherein the memory device comprises a two-terminal selector and a resistance variable storage element coupled to the two-terminal selector, and the operation method comprises:
providing a voltage pulse to the memory device in an operation cycle, wherein a voltage applied across the two-terminal selector during a falling part of the voltage pulse falls below a holding voltage of the two-terminal selector, a critical voltage falling rate of the falling part at which the voltage applied across the two-terminal selector reaches the holding voltage is from 100 MV/s to 10 GV/s, and the falling part of the voltage pulse declines by multiple steps; and
repeating the operation cycle, wherein a threshold voltage drift of the two-terminal selector during the operation cycles is less than 0.5 V.