US 11,990,181 B2
Low-power static random access memory
Katsuyuki Sato, Tokyo (JP); William Martin Snelgrove, Toronto (CA); and Saijagan Saijagan, Whitby (CA)
Assigned to UNTETHER AI CORPORATION, Toronto (CA)
Appl. No. 18/251,251
Filed by UNTETHER AI CORPORATION, Toronto (CA)
PCT Filed Jun. 21, 2022, PCT No. PCT/IB2022/055759
§ 371(c)(1), (2) Date May 1, 2023,
PCT Pub. No. WO2022/269492, PCT Pub. Date Dec. 29, 2022.
Claims priority of provisional application 63/213,393, filed on Jun. 22, 2021.
Prior Publication US 2023/0395142 A1, Dec. 7, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 5/14 (2013.01); G11C 7/1048 (2013.01); G11C 7/12 (2013.01); G11C 7/18 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A static random-access memory comprising:
at least one six-transistor memory cell arranged between a first bitline, a second bitline and a word line;
a bitline precharge circuit for precharging the first bitline and second bitline to a voltage of Vdd/2 prior to the at least one six-transistor memory cell receiving a word line signal;
a main amplifier for receiving signals on data lines din and /din in a first voltage domain via a gate WEi; and
a main amplifier precharge circuit for precharging the main amplifier in response to a signal /PEMA such that the main amplifier amplifies signals in the first voltage domain to a second voltage domain, wherein the main amplifier precharge circuit precharges the global bit line busses GBL and /GBL before the main amplifier receives signals on data lines din and /din and independently of the bitline precharge circuit precharging the first bitline and second bitline, wherein a plurality of six-transistor memory cells along a selected word line are simultaneously read or written, wherein the main amplifier also functions as a cache memory.