US 11,990,180 B2
Memory device
Shih-Lien Linus Lu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 28, 2022, as Appl. No. 17/587,075.
Application 17/587,075 is a continuation of application No. 16/657,323, filed on Oct. 18, 2019, granted, now 11,238,923.
Prior Publication US 2022/0157375 A1, May 19, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/419 (2006.01); G11C 5/14 (2006.01); G11C 11/418 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 5/148 (2013.01); G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a cell array comprising a plurality of cells, each of the plurality of cells operative to store one bit value; and
a reset circuit connected to the cell array, the reset circuit being operative to:
generate a reset signal as a logical disjunction of a first signal indicating an initiation of a power up duration of the plurality of cells and a second signal indicating a completion of the power up duration of the plurality of cells of the cell array; and
trigger, through the reset signal, a reset of a bit value stored in each of the plurality of cells of the cell array to a predetermined bit value in parallel during the power up duration.