| CPC G11C 11/419 (2013.01) [G11C 11/418 (2013.01)] | 6 Claims |
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1. A memory device accessed by circuits operating based on a first supply voltage, the memory device comprising:
a cell array electrically connected to a plurality of word lines and a plurality of bit lines;
a row driver configured to select one of the plurality of word lines based on a row address;
a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage;
a column driver configured to select a first bit line from the plurality of bit lines based on a column address; and
a read circuit configured to read data stored in the cell array through the first bit line; and
a control logic configured to generate the row address and the column address,
wherein the cell array, the row driver, the column driver, the read circuit and the control logic are configured to operate based on a second supply voltage, which is higher than the first supply voltage,
wherein the read circuit comprises a sense amplifier electrically connected to the first bit line and a second bit line complementary to the first bit line, from among the plurality of bit lines, and
wherein, when reading data stored in the cell array, the read circuit is configured to
shift a voltage difference between the first bit line and the second bit line from the first supply voltage to the second supply voltage,
output the shifted voltage difference as a first output signal and a second output signal, which is an inverse signal of the first output signal,
invert the first output signal and the second output signal based on the second supply voltage, and
invert the second output signal based on the first supply voltage.
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