US 11,990,177 B2
Multi-die memory device
Scott C. Best, Palo Alto, CA (US); and Ming Li, Fremont, CA (US)
Assigned to Rambus Inc., San Jose, CA (US)
Filed by Rambus Inc., San Jose, CA (US)
Filed on May 10, 2023, as Appl. No. 18/195,877.
Application 18/195,877 is a continuation of application No. 17/540,950, filed on Dec. 2, 2021, granted, now 11,657,868.
Application 17/540,950 is a continuation of application No. 17/135,112, filed on Dec. 28, 2020, granted, now 11,195,572, issued on Dec. 7, 2021.
Application 17/135,112 is a continuation of application No. 16/823,122, filed on Mar. 18, 2020, granted, now 10,885,971, issued on Jan. 5, 2021.
Application 16/823,122 is a continuation of application No. 16/211,966, filed on Dec. 6, 2018, granted, now 10,607,691, issued on Mar. 31, 2020.
Application 16/211,966 is a continuation of application No. 15/809,925, filed on Nov. 10, 2017, granted, now 10,157,660, issued on Dec. 18, 2018.
Application 15/809,925 is a continuation of application No. 15/098,269, filed on Apr. 13, 2016, granted, now 9,818,470, issued on Nov. 14, 2017.
Application 15/098,269 is a continuation of application No. 14/797,057, filed on Jul. 10, 2015, granted, now 9,324,411, issued on Apr. 26, 2016.
Application 14/797,057 is a continuation of application No. 14/278,655, filed on May 15, 2014, granted, now 9,082,463, issued on Jul. 14, 2015.
Application 14/278,655 is a continuation of application No. 13/562,242, filed on Jul. 30, 2012, granted, now 8,737,106, issued on May 27, 2014.
Application 13/562,242 is a continuation of application No. 12/519,353, granted, now 8,233,303, issued on Jul. 31, 2012, previously published as PCT/US2007/087359, filed on Dec. 13, 2007.
Claims priority of provisional application 60/870,065, filed on Dec. 14, 2006.
Prior Publication US 2023/0360694 A1, Nov. 9, 2023
Int. Cl. G11C 5/02 (2006.01); G11C 5/04 (2006.01); G11C 11/406 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01); H01L 25/10 (2006.01); H01L 25/18 (2023.01); H01L 23/00 (2006.01)
CPC G11C 11/4093 (2013.01) [G11C 5/02 (2013.01); G11C 5/025 (2013.01); G11C 5/04 (2013.01); G11C 11/406 (2013.01); G11C 11/4096 (2013.01); H01L 23/481 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/105 (2013.01); H01L 25/18 (2013.01); H01L 24/73 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48225 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06558 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01055 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/3011 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a logic integrated circuit (IC) base die, the logic IC base die including a primary interface for communicating with memory control circuitry, and multiple independent secondary interfaces; and
multiple memory die stacked on the logic IC base die, each of the multiple memory die including at least one independent memory interface coupled to a corresponding one of the multiple independent secondary interfaces of the logic IC base die in a dedicated manner using through-silicon-via (TSV) paths.