US 11,990,176 B2
Pre-decoder circuity
Jin Seung Son, McKinney, TX (US); and Mingdong Cui, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 2, 2022, as Appl. No. 17/831,332.
Prior Publication US 2023/0395129 A1, Dec. 7, 2023
Int. Cl. G11C 13/00 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/4087 (2013.01) [G11C 11/4074 (2013.01); G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory array including a plurality of memory cells;
decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate; and
pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises:
a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells; and
zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells;
wherein the pre-decoder circuitry comprises:
first pre-decoder circuitry configured to provide the positive voltage for the first gate and the zero volts for the first gate; and
second pre-decoder circuitry configured to provide the negative voltage for the second gate.