US 11,990,172 B2
Refresh command control for host assist of row hammer mitigation
Bill Nale, Livermore, CA (US); and Christopher E. Cox, Placerville, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 22, 2023, as Appl. No. 18/213,231.
Application 17/157,826 is a division of application No. 16/370,578, filed on Mar. 29, 2019, granted, now 10,950,288, issued on Mar. 16, 2021.
Application 18/213,231 is a continuation of application No. 17/686,287, filed on Mar. 3, 2022, granted, now 11,688,452.
Application 17/686,287 is a continuation of application No. 17/157,826, filed on Jan. 25, 2021, granted, now 11,282,561, issued on Mar. 22, 2022.
Prior Publication US 2023/0386548 A1, Nov. 30, 2023
Int. Cl. G11C 11/406 (2006.01); G06F 3/06 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 11/40611 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G11C 11/4096 (2013.01); G11C 11/40618 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM) device, comprising:
rows of memory to be refreshed during normal operation; and
input/output (I/O) hardware to receive an additional refresh command in a period of high access to the rows of memory as indicated by a count of activate commands received, the additional refresh command to be in excess of a number of refresh commands necessary to refresh the rows of memory within a refresh window, the additional refresh command to provide additional refresh time during the refresh window for the DRAM device to manage refresh internally, including the DRAM device to internally indicate an address for refresh.