US 11,990,169 B2
Transistorless memory cell
Katherine Chiang, New Taipei (TW); Chung Te Lin, Tainan (TW); Min Cao, Martinez, CA (US); Yuh-Jier Mii, Hsin-Chu (TW); and Sheng-Chih Lai, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 3, 2021, as Appl. No. 17/392,583.
Application 17/392,583 is a continuation of application No. 16/122,057, filed on Sep. 5, 2018, granted, now 11,094,361.
Prior Publication US 2021/0366529 A1, Nov. 25, 2021
Int. Cl. G11C 11/16 (2006.01); H10B 61/00 (2023.01); H10N 50/01 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01)
CPC G11C 11/1659 (2013.01) [G11C 11/161 (2013.01); H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); H10N 50/85 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated chip, comprising:
an operative memory device coupled to a bit-line, wherein the operative memory device is configured to store a data state;
a regulating access apparatus coupled between the operative memory device and a first word-line, wherein the regulating access apparatus comprises one or more regulating MTJ devices that are configured to control a current provided to the operative memory device; and
wherein the one or more regulating MTJ devices respectively comprise a free layer, a dielectric barrier layer on the free layer, and a pinned layer separated from the free layer by the dielectric barrier layer, wherein the pinned layer covers a center of an entire upper surface of the dielectric barrier layer, the entire upper surface of the dielectric barrier layer facing towards the pinned layer and extending between opposing outermost sidewalls of the dielectric barrier layer.