US 11,990,095 B2
Display module which prevents signal lines from being damaged
Jaemin Shin, Suwon-si (KR); Sangwoo Kim, Seoul (KR); Gyujeong Lee, Anyang-si (KR); Hyejin Joo, Suwon-si (KR); and Jongho Hong, Yongin-si (KR)
Assigned to Samsung Display Co., Ltd., Yongin-Si (KR)
Filed by Samsung Display Co., Ltd., Yongin-Si (KR)
Filed on Apr. 7, 2022, as Appl. No. 17/715,345.
Application 17/715,345 is a continuation of application No. 16/830,174, filed on Mar. 25, 2020, granted, now 11,341,921.
Claims priority of application No. 10-2019-0033977 (KR), filed on Mar. 26, 2019.
Prior Publication US 2022/0230595 A1, Jul. 21, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G09G 3/30 (2006.01); G06F 1/16 (2006.01); G09F 9/30 (2006.01); G09G 3/3266 (2016.01); G09G 3/3291 (2016.01); G09G 3/36 (2006.01)
CPC G09G 3/3266 (2013.01) [G06F 1/1652 (2013.01); G09F 9/301 (2013.01); G09G 3/3291 (2013.01); G09G 2380/02 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A display module, comprising:
a base including a plurality of unit portions, each of the plurality of unit portions including a first portion and a plurality of second portions extending from the first portion and connecting adjacent first portions;
a gate pattern overlapped with the first portion, the gate pattern not extending over the plurality of second portions;
a first insulating layer disposed on the base to cover the gate pattern, the first insulating layer being overlapped with the first portion and the plurality of second portions and comprising a first contact hole defined therein;
a plurality of first lines which are disposed on the first insulating layer, each of the plurality of first lines being overlapped with at least one of the plurality of second portions, and at least one of the plurality of first lines being electrically connected to the gate pattern through the first contact hole;
a second insulating layer disposed on the plurality of first lines;
a plurality of second lines which are disposed on the second insulating layer, each of the plurality of second lines being overlapped with at least one of the plurality of second portions;
a third insulating layer disposed on the plurality of second lines; and
a plurality of third lines which are disposed on the third insulating layer, each of the plurality of third lines being overlapped with at least one of the plurality of second portions,
wherein the gate pattern comprises a first conductive material and each of the plurality of first lines, the plurality of second lines, and the plurality of third lines comprises a conductive material different from the first conductive material.