US 11,990,089 B2
Display substrate and manufacturing method thereof, display device
Pengfei Yu, Beijing (CN); Lu Bai, Beijing (CN); Jie Dai, Beijing (CN); Mengqi Wang, Beijing (CN); Huijun Li, Beijing (CN); Yupeng He, Beijing (CN); Hao Zhang, Beijing (CN); Meng Zhang, Beijing (CN); and Xin Zhang, Beijing (CN)
Assigned to CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Chengdu (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed by CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Sichuan (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Filed on Jun. 26, 2023, as Appl. No. 18/341,056.
Application 18/341,056 is a continuation of application No. 17/599,198, granted, now 11,735,107, previously published as PCT/CN2020/084246, filed on Apr. 10, 2020.
Prior Publication US 2023/0335051 A1, Oct. 19, 2023
Int. Cl. G09G 3/3225 (2016.01); G11C 19/28 (2006.01); H10K 59/121 (2023.01); H10K 59/124 (2023.01); H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 59/12 (2023.01)
CPC G09G 3/3225 (2013.01) [G11C 19/28 (2013.01); H10K 59/1213 (2023.02); H10K 59/124 (2023.02); H10K 59/131 (2023.02); H10K 71/00 (2023.02); G09G 2300/0426 (2013.01); G09G 2310/0286 (2013.01); H10K 59/1201 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A display substrate, comprising a base substrate, and a shift register unit, a first clock signal line, and a second clock signal line that are provided on the base substrate,
wherein the first clock signal line extends along a first direction on the base substrate and is configured to provide a first clock signal to the shift register unit;
the second clock signal line extends along the first direction on the base substrate and is configured to provide a second clock signal to the shift register unit;
the shift register unit comprises an input circuit, an output circuit, a first control circuit, a second control circuit, and an output control circuit;
the input circuit is configured to input an input signal to a first node in response to the first clock signal;
the output circuit is configured to output an output signal to an output terminal;
the first control circuit is configured to control a level of a second node in response to a level of the first node and the first clock signal;
the second control circuit is connected to the first node and the second node, and is configured to control the level of the first node under control of the level of the second node and the second clock signal;
the output control circuit is configured to control a level of the output terminal under control of the level of the second node;
the first control circuit comprises a first control transistor and a second control transistor, and the second control circuit comprises a first noise reduction transistor and a second noise reduction transistor;
an active layer of the first control transistor, an active layer of the first noise reduction transistor, and an active layer of the second noise reduction transistor are arranged side by side in a second direction different from the first direction; and
the input circuit comprises an input transistor, the input transistor and the first noise reduction transistor are sequentially arranged in the first direction, and an imaginary line of a channel region of the first noise reduction transistor extending in the second direction does not intersect with an imaginary line of an active layer of the input transistor extending in the second direction.