US 11,989,874 B2
Multi-tier PCBA integrity validation process
Khiam Foh Lo, Singapore (SG)
Assigned to Hewlett Packard Enterprise Development LP, Spring, TX (US)
Filed by Hewlett Packard Enterprise Development LP, Houston, TX (US)
Filed on Jan. 14, 2022, as Appl. No. 17/576,481.
Prior Publication US 2023/0230225 A1, Jul. 20, 2023
Int. Cl. G06T 7/00 (2017.01)
CPC G06T 7/001 (2013.01) [G06T 2207/30141 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
storing a first template which comprises an image of a first validated printed circuit board;
storing a first image of an unvalidated printed circuit board captured prior to shipping of the unvalidated printed circuit board from a first site to a second site;
generating a second template which comprises an image of a second validated printed circuit board corresponding to the first validated printed circuit board;
capturing a second image of the unvalidated printed circuit board subsequent to arrival of the unvalidated printed circuit board at the second site;
capturing a third image of the unvalidated printed circuit board prior to installation of the unvalidated printed circuit board into a computer system or an assembly line; and
detecting an anomaly associated with the unvalidated printed circuit board based on results of one or more of:
a first comparison between the first template and the second template;
a second comparison between the first image and the first template;
a third comparison between the second image and the second template;
a fourth comparison between the third image and the second template;
a fifth comparison between the first image and the second image;
a sixth comparison between the first image and the third image; and
a seventh comparison between the second image and the third image.