CPC G06N 3/04 (2013.01) [G06F 1/3296 (2013.01); G06N 3/08 (2013.01)] | 20 Claims |
1. A neural processor circuit, comprising:
a plurality of neural engine circuits that are each configured for selective activation, each of the neural engine circuits configured to perform convolution operations on input data and kernel coefficients to generate output data, at least two of the neural engine circuits each comprising a plurality of multiply-add (MAD) circuits;
a neural task manager circuit configured to provide configuration data to the neural engine circuits to activate or deactivate one or more of the neural engine circuits for a task;
a kernel direct memory access (DMA) circuit configured to send kernel data to activated neural engine circuits of the neural engine circuits; and
a data buffer having a scalable size that is based on a number of the activated neural engine circuits.
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