US 11,989,600 B2
Method for an internal command from a plurality of processing cores with memory sub-system that cache identifiers for access commands
John Traver, Boise, ID (US); and Jay R. Shoen, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 15, 2022, as Appl. No. 17/945,673.
Application 17/945,673 is a continuation of application No. 16/841,935, filed on Apr. 7, 2020, granted, now 11,474,885.
Prior Publication US 2023/0014975 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 9/00 (2006.01); G06F 9/38 (2018.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/084 (2016.01); G06F 12/0871 (2016.01)
CPC G06F 9/544 (2013.01) [G06F 9/3836 (2013.01); G06F 9/546 (2013.01); G06F 12/0246 (2013.01); G06F 12/084 (2013.01); G06F 12/0871 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving an access command to perform an access operation on a transfer unit of a memory sub-system;
storing an identifier associated with the access command;
storing the identifier associated with an internal command in a shared memory that is accessible by a plurality of cores; and
issuing the internal command to perform the access operation on the memory sub-system.