US 11,989,599 B2
Isolating communication streams to achieve high performance multi-threaded communication for global address space programs
Mario Flajslik, Hudson, MA (US); and James Dinan, Hopkinton, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 21, 2020, as Appl. No. 16/880,277.
Application 16/880,277 is a continuation of application No. 14/670,733, filed on Mar. 27, 2015, granted, now 10,671,457.
Prior Publication US 2021/0255910 A1, Aug. 19, 2021
Int. Cl. G06F 9/54 (2006.01); G06F 9/52 (2006.01)
CPC G06F 9/544 (2013.01) [G06F 9/52 (2013.01)] 30 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
processor circuitry including first and second cores;
message monitor circuitry to detect a first outbound communication and a second outbound communication from the first core to the second core;
context manager circuitry to:
identify a first context assigned to the first outbound communication, the first context associated with a first process to be executed on the second core, the first outbound communication to trigger a notification; and
identify a second context assigned to the second outbound communication, the second context associated with a second process to be executed on the second core, the second context equal to the first context when operations of the second process are the same as operations of the first process, the second context different than the first context when the operations of the second process are different than the operations of the first process; and
logic circuitry to control access to data in a memory space based on one or more logic values associated with one or more access count values, the memory space shared by the first and second cores.