US 11,989,583 B2
Circuitry and method
Chris Abernathy, Austin, TX (US); Eric Charles Quinnell, Austin, TX (US); Abhishek Raja, Austin, TX (US); and Michael David Achenbach, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Mar. 31, 2021, as Appl. No. 17/218,425.
Prior Publication US 2022/0318051 A1, Oct. 6, 2022
Int. Cl. G06F 9/48 (2006.01); G06F 9/50 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 9/48 (2013.01); G06F 9/4843 (2013.01); G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5027 (2013.01); G06F 9/5033 (2013.01); G06F 9/5038 (2013.01)] 17 Claims
OG exemplary drawing
 
1. Circuitry comprising:
two or more clusters of execution units, each cluster comprising one or more execution units to execute processing instructions; and
scheduler circuitry to maintain two or more queues of processing instructions, the scheduler circuitry comprising picker circuitry to:
select, from a respective queue of the two or more queues, respective queued processing instructions for issue to execution units of the two or more clusters of execution units; and
select, from another respective queue of the two or more queues, respective queued processing instructions for issue to execution units of the two or more clusters of execution units,
in which:
the scheduler circuitry is configured to maintain dependency data associated with each queued processing instruction, the dependency data for a queued processing instruction indicating any source operands which are required to be available for use in execution of that queued processing instruction and to inhibit issue of that queued processing instruction until all of the required source operands for that queued processing instruction are available and is configured to be responsive to an indication of the availability of a given operand as a source operand for use in execution of queued processing instructions;
the scheduler circuitry is responsive to an indication of availability of one or more last awaited source operands for a given queued processing instruction, to inhibit for at least one clock cycle selection by the picker circuitry of the given queued processing instruction for issue to an execution unit in a cluster of the two or more clusters of execution units other than a cluster of the two or more clusters of execution units containing an execution unit which generated at least one of those last awaited source operands;
the scheduler circuitry is responsive to completion of the at least one clock cycle to enable selection by the picker circuitry of the given queued processing instruction for issue to the execution unit in the cluster of the two or more clusters of execution units other than the cluster of the two or more clusters of execution units containing the execution unit which generated at least one of those last awaited source operands.