US 11,989,582 B2
Apparatus and method for low-latency decompression acceleration via a single job descriptor
James Guilford, Northborough, MA (US); George Powley, Northborough, MA (US); Vinodh Gopal, Westborough, MA (US); and Wajdi Feghali, Boston, MA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 26, 2020, as Appl. No. 17/033,760.
Prior Publication US 2022/0100526 A1, Mar. 31, 2022
Int. Cl. G06F 9/38 (2018.01); G06F 9/48 (2006.01)
CPC G06F 9/4881 (2013.01) [G06F 9/3887 (2013.01); G06F 2209/483 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a plurality of job descriptor queues to store job descriptors describing work to be performed;
enqueue circuitry to receive a first job descriptor, the first job descriptor comprising a plurality of fields including a first field to store a Single Instruction Multiple Data (SIMD) width, wherein when the SIMD width indicates that the first job descriptor is an SIMD job descriptor and the SIMD width is less than or equal to a number of open job descriptor slots in the plurality of job descriptor queues, the enqueue circuitry is to generate a plurality of job descriptors based on fields of the first job descriptor and store the plurality of job descriptors in the open job descriptor slots of the plurality of job descriptor queues; and
one or more processing pipelines to process job descriptors stored in the plurality of job descriptor queues to perform the work described, wherein at least some of the plurality of job descriptors generated from the first job descriptor are processed in parallel by the one or more processing pipelines.