US 11,989,563 B2
Dynamic bios policy for hybrid graphics platforms
Subrata Banik, Bangalore (IN); Rajaram Regupathy, Bangalore (IN); and Kalyan Kondapally, Hillsboro, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 4, 2020, as Appl. No. 17/111,989.
Prior Publication US 2021/0089326 A1, Mar. 25, 2021
Int. Cl. G06F 9/4401 (2018.01); G06F 1/26 (2006.01); G06F 1/3212 (2019.01); G06F 9/451 (2018.01); G06F 11/30 (2006.01); G06F 15/78 (2006.01)
CPC G06F 9/4406 (2013.01) [G06F 1/3212 (2013.01); G06F 9/4403 (2013.01); G06F 9/451 (2018.02); G06F 11/3013 (2013.01); G06F 11/3062 (2013.01); G06F 15/7807 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A computing system comprising:
an embedded controller (EC);
a system on chip (SoC);
an integrated graphics processor;
an integrated display coupled to the integrated graphics processor;
a discrete graphics processor;
a root port coupled to the discrete graphics processor; and
a memory including a set of executable program instructions, which when executed by the SoC, cause the SoC to:
detect a low battery condition in the computing system during a pre-boot stage of the computing system,
disable the root port in response to the low battery condition,
conduct an initialization of the integrated display while the root port is disabled, and
enable the root port in response to a successful negotiation of increased power by a verified read write code of the EC.