CPC G06F 9/3004 (2013.01) [G06F 9/325 (2013.01); G06F 9/466 (2013.01); G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 15/781 (2013.01)] | 20 Claims |
1. An apparatus comprising:
a memory controller;
a memory array coupled to the memory controller;
a programmable atomic unit coupled to the memory controller and comprising a processor, the processor configured to perform operations comprising:
receive a request from a requesting processor, the request requesting execution of a programmable atomic transaction at the programmable atomic unit of the memory controller, the request including an identifier of the programmable atomic transaction;
locate instructions of the programmable atomic transaction in a memory of the programmable atomic unit based upon the identifier;
execute the instructions of the programmable atomic transaction, starting at a first instruction, the executing comprising incrementing an instruction counter for every executed instruction;
determine that the instruction counter exceeded a specified instruction execution limit; and
responsive to determining that the instruction counter exceeded the specified instruction execution limit, terminating execution of the programmable atomic transaction.
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