US 11,989,555 B2
Instructions for remote atomic operations
Doddaballapur N. Jayasimha, Saratoga, CA (US); Jonas Svennebring, Sollentuna (SE); Samantika S. Sury, Westford, MA (US); Christopher J. Hughes, Santa Clara, CA (US); Jong Soo Park, Santa Clara, CA (US); and Lingxiang Xiang, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2017, as Appl. No. 15/638,120.
Prior Publication US 2019/0004810 A1, Jan. 3, 2019
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/46 (2006.01); G06F 13/28 (2006.01)
CPC G06F 9/3004 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30185 (2013.01); G06F 9/3836 (2013.01); G06F 9/46 (2013.01); G06F 13/28 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A processor comprising:
fetch circuitry configured to fetch an instruction from a code storage, the instruction comprising an opcode, a source identifier, and a destination identifier;
decode circuitry configured to decode the fetched instruction; and
a scheduling circuit configured to select an execution circuit among multiple circuits to execute the instruction,
wherein the execution circuit is configured to execute the decoded instruction, the execution comprising atomically reading a datum from a location identified by the destination identifier, performing an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and writing a result of the operation back to the location identified by the destination identifier, and the instruction has an out of order ordering requirement for memory loads and stores when the location is not a register, and the instruction has an in order ordering requirement for memory loads and stores when the location is a destination register.