| CPC G06F 9/3001 (2013.01) [G06F 7/58 (2013.01); G06F 9/30036 (2013.01); G06F 16/137 (2019.01); G06F 16/2255 (2019.01); H01L 27/0688 (2013.01)] | 17 Claims |
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1. A device comprising:
a memory that is column addressable;
a processor comprising circuitry connected to the memory, wherein the circuitry is to:
add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix, wherein multiplying each input data vector with a projection matrix comprises operations to:
normalize input data from the set of input data vectors to add invariance to one or more specific deformations;
project the normalized input data to a different dimensional space to form a dimensionally expanded projection matrix;
binarize the dimensionally expanded projection matrix to produce a binary dimensionally expanded projection matrix corresponding with a binary dimensionally expanded hash code;
adapt a binary sparse projection matrix via procrustean orthogonal sparse hashing, the procrustean orthogonal sparse hashing comprising operations to: multiply each input data vector with a projection matrix having values optimized for the input data in the set of input data vectors by alternatingly iterating between optimizing the binary dimensionally expanded hash code and optimizing the binary dimensionally expanded projection matrix until the binary dimensionally expanded hash code and the binary dimensionally expanded projection matrix have converged to corresponding target values, wherein the procrustean orthogonal sparse hashing bypasses usage of random values in the binary sparse projection matrix during iterative computation of the binary dimensionally expanded hash code;
produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix; and
determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.
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