US 11,989,531 B2
Device and method with multi-bit operation
Sungmeen Myung, Suwon-si (KR); Seungchul Jung, Suwon-si (KR); and Sangjoon Kim, Hwaseong-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 13, 2021, as Appl. No. 17/473,139.
Claims priority of application No. 10-2021-0048025 (KR), filed on Apr. 13, 2021.
Prior Publication US 2022/0326910 A1, Oct. 13, 2022
Int. Cl. G06F 7/50 (2006.01); G06F 7/523 (2006.01); G06N 3/065 (2023.01); G11C 11/56 (2006.01); H03M 1/38 (2006.01)
CPC G06F 7/50 (2013.01) [G06F 7/523 (2013.01); G06N 3/065 (2023.01); G11C 11/56 (2013.01); H03M 1/38 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A multi-bit cell comprising:
a memory storing weight resistances corresponding to multi-bit weights;
a current source configured to apply a current to the memory to generate a weight voltage from a respective weight resistance;
a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to:
receive a different bit of a multi-bit input; and
in response to the different bit, output one signal from either the weight voltage or a first fixed voltage; and
a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to:
store a respective weight capacitance; and
generate charge data by performing an operation on the outputted one signal and the respective weight capacitance.