US 11,989,459 B2
Semiconductor memory device and test system including the same
Hongjun Jin, Hwaseong-si (KR); Yongjae Lee, Suwon-si (KR); Seunghan Kim, Yongin-si (KR); and Hyoungjoo Kim, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 1, 2022, as Appl. No. 18/073,079.
Application 18/073,079 is a continuation of application No. 17/375,168, filed on Jul. 14, 2021, granted, now 11,520,528.
Claims priority of application No. 10-2020-0174328 (KR), filed on Dec. 14, 2020.
Prior Publication US 2023/0091567 A1, Mar. 23, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 29/10 (2006.01); G11C 29/56 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0653 (2013.01); G06F 3/0673 (2013.01); G11C 29/10 (2013.01); G11C 29/56004 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells storing data;
a command/address generation circuit configured to generate a test read command and a test pattern data selection signal in response to receiving a test clock signal;
a test pattern data storage including a plurality of registers, each of the plurality of registers storing m-bit test pattern data, and configured to select first m-bit test pattern data from one of the plurality of registers in response to receiving the test read command and the test pattern data selection signal, wherein m is a natural number greater than 1;
a read path circuit configured to read stored m-bit data from the memory cell array; and
a test read data generation circuit configured to compare the first m-bit test pattern data and the m-bit data, and generate n-bit test data based on a comparison of the first m-bit test pattern data and the m-bit data, wherein n is a natural number greater than 1.