US 11,989,450 B2
Signal development caching in a memory device
Dmitri A. Yudanov, Rancho Cordova, CA (US); and Shanky Kumar Jain, Folsom, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/415,664
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Dec. 20, 2019, PCT No. PCT/US2019/067838
§ 371(c)(1), (2) Date Jun. 17, 2021,
PCT Pub. No. WO2020/132434, PCT Pub. Date Jun. 25, 2020.
Claims priority of provisional application 62/783,388, filed on Dec. 21, 2018.
Prior Publication US 2022/0076733 A1, Mar. 10, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 9/54 (2006.01); G06F 12/02 (2006.01); G06F 12/0802 (2016.01); G06F 12/0873 (2016.01); G06F 12/0875 (2016.01); G06F 12/0893 (2016.01); G06F 12/1045 (2016.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 8/08 (2006.01); G11C 11/22 (2006.01); G11C 11/406 (2006.01); G11C 11/4074 (2006.01); G11C 11/408 (2006.01); G11C 11/4091 (2006.01); G11C 11/4096 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 9/546 (2013.01); G06F 12/0246 (2013.01); G06F 12/0802 (2013.01); G06F 12/0873 (2013.01); G06F 12/0875 (2013.01); G06F 12/0893 (2013.01); G06F 12/1045 (2013.01); G11C 7/08 (2013.01); G11C 7/1012 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); G11C 8/08 (2013.01); G11C 11/221 (2013.01); G11C 11/2257 (2013.01); G11C 11/2259 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); G11C 11/2297 (2013.01); G11C 11/406 (2013.01); G11C 11/40603 (2013.01); G11C 11/4074 (2013.01); G11C 11/4085 (2013.01); G11C 11/4091 (2013.01); G11C 11/4096 (2013.01); G06F 2212/60 (2013.01); G06F 2212/608 (2013.01); G06F 2212/72 (2013.01); G06F 2212/7201 (2013.01)] 37 Claims
OG exemplary drawing
 
1. A method comprising:
receiving one or more commands corresponding to data of a first address of a memory array that comprises a plurality of memory cells;
determining, based at least in part on receiving the one or more commands, that the data of the first address of the memory array is stored in a cache block of a signal development cache at a second address of the signal development cache; and
transferring the data to one or more sense amplifiers based at least in part on determining that the data is stored at the second address of the signal development cache.