US 11,989,448 B2
Memory controller and memory system including the same
Jun Hee Ryu, Gyeonggi-do (KR); Kwang Jin Ko, Gyeonggi-do (KR); Chang Hyun Park, Gyeonggi-do (KR); and Young Pyo Joo, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Aug. 16, 2022, as Appl. No. 17/888,965.
Claims priority of application No. 10-2022-0037657 (KR), filed on Mar. 25, 2022.
Prior Publication US 2023/0305743 A1, Sep. 28, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/0658 (2013.01) [G06F 3/061 (2013.01); G06F 3/0653 (2013.01); G06F 3/0683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory controller for controlling heterogeneous first and second memory devices, each configured to include a plurality of pages, the memory controller comprising:
a scanning period controller configured to reset, whenever scanning points sequentially arrive, access information indicating whether each of the plurality of pages is accessed, and set a scanning interval for each of the pages between the scanning points for the page based on an attribute of the page;
an attribute determiner configured to determine, as a hot page or a cold page, the attribute of each of the pages based on an access interval for the page from a first scanning point among the scanning points for the page to a time at which access to data stored in the page is requested; and
a memory allocator configured to control the first memory device and the second memory device based on the attributes of the pages.