CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/064 (2013.01); G06F 3/0659 (2013.01); G06F 3/0673 (2013.01); G06F 12/0246 (2013.01); G06F 12/0871 (2013.01); G06F 2212/7201 (2013.01)] | 20 Claims |
1. A storage device comprising:
a memory device including a plurality of memory cells;
a memory controller configured to control an operation performed on the memory device; and
a buffer memory including a cache area and a mapping area in which mapping data indicating a mapping relationship between a logical block address and a physical block address corresponding to the operation is stored,
wherein the memory controller is configured to control the buffer memory to allocate a portion of the mapping area to the cache area according to an allocation request received from a host, and to store data except for the mapping data in the cache area, and
wherein the memory controller controls the buffer memory to allocate the portion by adjusting the cache area according to data throughput of an internal device of the host.
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