US 11,989,442 B2
Semiconductor integrated circuit, reception device, memory system, and semiconductor storage device for reducing power consumption of equalizer
Shinichi Ikeda, Fujisawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 15, 2021, as Appl. No. 17/644,435.
Claims priority of application No. 2021-104418 (JP), filed on Jun. 23, 2021.
Prior Publication US 2022/0413745 A1, Dec. 29, 2022
Int. Cl. G11C 7/22 (2006.01); G06F 3/06 (2006.01); G11C 7/10 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/32 (2006.01); H03G 3/30 (2006.01); H04L 7/00 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G11C 7/1048 (2013.01); G11C 7/1066 (2013.01); G11C 7/1093 (2013.01); G11C 7/222 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01); H03G 3/3036 (2013.01); H04L 7/0079 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a reception circuit configured to receive a strobe signal of which a logic is intermittently switched in synchronization with a data signal and change a boost amount of at least a high frequency component of the received strobe signal;
an output circuit configured to extract a low frequency component including at least a DC component of the strobe signal received by the reception circuit and to output a first signal; and
a comparison circuit configured to compare a signal level of the first signal with a threshold level,
wherein the reception circuit is configured to change the boost amount of at least the high frequency component of the strobe signal based on a comparison result obtained by the comparison circuit.