US 11,989,440 B2
Hybrid memory system configurable to store neural memory weight data in analog form or digital form
Hieu Van Tran, San Jose, CA (US)
Assigned to SILICON STORAGE TECHNOLOGY, INC., San Jose, CA (US)
Filed by Silicon Storage Technology, Inc., San Jose, CA (US)
Filed on Nov. 4, 2021, as Appl. No. 17/519,241.
Claims priority of provisional application 63/232,149, filed on Aug. 11, 2021.
Prior Publication US 2023/0053608 A1, Feb. 23, 2023
Int. Cl. G11C 7/16 (2006.01); G06F 3/06 (2006.01); G06N 3/065 (2023.01); G11C 7/10 (2006.01); G11C 11/54 (2006.01); G11C 27/00 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01); G06N 3/065 (2023.01); G11C 7/1006 (2013.01); G11C 7/16 (2013.01); G11C 11/54 (2013.01); G11C 27/005 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A system comprising:
an array of non-volatile memory cells arranged into rows and columns;
configurable input circuitry coupled to the array to provide an input to the array, wherein the configurable input circuitry comprises a row register and a digital-to-analog converter block for use in a first mode and a row decoder block for use in a second mode; and
configurable output circuitry coupled to the array to provide an output received from the array in response to the input;
wherein in the first mode, the configurable output circuitry provides digital data from the array; and
wherein in the second mode, the configurable output circuitry provides analog data from the array.