US 11,989,427 B2
Transistor configurations for vertical memory arrays
Ferdinando Bedeschi, Biassono (IT)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Aug. 30, 2022, as Appl. No. 17/823,371.
Claims priority of provisional application 63/365,683, filed on Jun. 1, 2022.
Prior Publication US 2023/0393766 A1, Dec. 7, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0625 (2013.01) [G06F 3/0629 (2013.01); G06F 3/0673 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a conductive pillar extending through a plurality of levels of a memory array, wherein, at each level of the plurality of levels, one or more memory cells of the memory array are coupled between the conductive pillar and a respective word line;
a first transistor operable to couple the conductive pillar with a first bit line based at least in part on a first voltage at a gate of the first transistor; and
a second transistor operable to couple the conductive pillar with a second bit line based at least in part on a second voltage at a gate of the second transistor.