US 11,989,425 B2
Apparatus and method for controlling access to a set of memory mapped control registers
Thomas Christopher Grocutt, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 17/759,426
Filed by Arm Limited, Cambridge (GB)
PCT Filed Dec. 21, 2020, PCT No. PCT/GB2020/053326
§ 371(c)(1), (2) Date Jul. 25, 2022,
PCT Pub. No. WO2021/152282, PCT Pub. Date Aug. 5, 2021.
Claims priority of application No. 2001276 (GB), filed on Jan. 30, 2020.
Prior Publication US 2023/0056039 A1, Feb. 23, 2023
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01); G06F 12/14 (2006.01)
CPC G06F 3/0622 (2013.01) [G06F 3/0637 (2013.01); G06F 3/0673 (2013.01); G06F 12/1466 (2013.01)] 22 Claims
OG exemplary drawing
 
21. A method of controlling access to a set of memory mapped control registers within an apparatus, comprising:
executing program code on processing circuitry to perform data processing operations;
storing, within the set of memory mapped control registers, control information used to control operation of the processing circuitry when executing the program code;
storing within a lockdown register a lockdown value;
executing store instructions on the processing circuitry in order to perform write operations to a memory address space, the store instructions being of multiple types; and
when the lockdown value is set, preventing a write operation being performed to change the control information in the memory mapped control registers unless that write operation occurs due to execution by the processing circuitry of a store instruction from a first subset of the multiple types of store instructions; wherein
the control information stored in the memory mapped control registers comprises at least control information used to control which regions of the memory address space are accessible to trusted program code and untrusted program code; and
the processing circuitry is arranged to allow the trusted program code to update the lockdown value in the lockdown register, and is arranged to use the lockdown value to control performance of write operations to the memory mapped control registers by at least the trusted program code.