CPC G06F 16/587 (2019.01) [G06F 16/219 (2019.01); G11C 11/5614 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/77 (2013.01)] | 20 Claims |
1. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
applying a voltage pulse to the memory cell;
determining the memory cell snaps back in response to the applied voltage pulse;
turning off a current to the memory cell upon determining the memory cell snaps back; and
applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the number of additional voltage pulses have a same magnitude.
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