US 11,989,228 B2
Multi-state programming of memory cells
Jeremy M. Hirst, Orangevale, CA (US); Shanky K. Jain, Folsom, CA (US); Hernan A. Castro, Shingle Springs, CA (US); Richard K Dodge, Santa Clara, CA (US); and William A. Melton, Shingle Springs, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 15, 2021, as Appl. No. 17/526,121.
Application 17/526,121 is a continuation of application No. 16/729,787, filed on Dec. 30, 2019, granted, now 11,177,009.
Prior Publication US 2022/0075817 A1, Mar. 10, 2022
Int. Cl. G06F 16/587 (2019.01); G06F 16/21 (2019.01); G11C 11/56 (2006.01); G11C 13/00 (2006.01)
CPC G06F 16/587 (2019.01) [G06F 16/219 (2019.01); G11C 11/5614 (2013.01); G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 2213/77 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a memory having a plurality of memory cells; and
circuitry configured to program a memory cell of the plurality of memory cells to one of at least three possible data states by:
applying a voltage pulse to the memory cell;
determining the memory cell snaps back in response to the applied voltage pulse;
turning off a current to the memory cell upon determining the memory cell snaps back; and
applying a number of additional voltage pulses to the memory cell after turning off the current to the memory cell, wherein each of the number of additional voltage pulses have a same magnitude.