CPC G06F 15/8015 (2013.01) [G06F 9/3001 (2013.01); G06F 9/30047 (2013.01); G06F 9/3887 (2013.01); G06F 1/32 (2013.01); G06N 3/04 (2013.01); G06N 3/08 (2013.01)] | 8 Claims |
1. A computing device comprising:
a plurality of rows of processing elements to perform single instruction multiple data (SIMD) operations, wherein the processing elements of each row are mutually connected to share data;
a row arithmetic logic unit (ALU) at each row of the plurality of rows of processing elements, the row ALU of a respective row being configured to perform an operation with processing elements of the respective row, wherein the row ALU is connected to a plurality of end-most processing elements of the respective row; and
a bank ALU connected to the row ALU of each row of processing elements, the bank ALU being configured to perform an additional operation with results obtained by row ALUs of the plurality of rows of processing elements.
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