CPC G06F 13/4282 (2013.01) | 5 Claims |
1. A universal asynchronous receiver transmitter (UART) interface circuit, comprising:
a master transmit (TX) input, a master receive (RX) output, a first slave input/output (I/O), a second slave I/O, and an enable (EN) input;
an inverter configured to logically invert a signal at the EN input;
a first single-pole, double-throw (SPDT) switch having a normally closed (NC) terminal, a normally open (NO) terminal, a common (COM) terminal, and a control (CTRL) input, wherein the NC terminal is connected with the master TX input and the NO terminal is connected with the master RX output;
a second SPDT switch having an NC terminal, an NO terminal, a COM terminal, and a CTRL input, wherein the NC terminal is connected with the master TX input and the NO terminal is connected with the master RX output;
a third SPDT switch having an NC terminal, an NO terminal, a COM terminal, and a CTRL input, wherein the NC terminal is connected with the COM terminal of the first SPDT switch, the COM terminal is connected with the first slave terminal, and the NO terminal is left unconnected;
a fourth SPDT switch having an NC terminal, an NO terminal, a COM terminal, and a CTRL input, wherein the NC terminal is connected with the COM terminal of the second SPDT switch, the COM terminal is connected with the second slave terminal, and the NO terminal is left unconnected;
a first retriggerable monoshot having a Q output, an nQ output that is a logical inverse of the Q output, a clock (CLK) input, and a reset input, wherein the CLK input is connected with the first slave terminal, and wherein the Q output remains a logic 1 for a hold time after a triggering of the first retriggerable monoshot;
a second retriggerable monoshot having a Q output, an nQ output, a CLK input, and a reset input, wherein the CLK input is connected with the second slave terminal, and wherein the Q output remains a logic 1 for the hold time after a triggering of the second retriggerable monoshot;
a first AND gate configured to logically AND the Q output of the first retriggerable monoshot and the nQ output of the second retriggerable monoshot, wherein an output of the first AND gate drives the CTRL input of the first SPDT switch;
a second AND gate configured to logically AND the Q output of the second retriggerable monoshot and the nQ output of the first retriggerable monoshot, wherein an output of the second AND gate drives the CTRL input of the second SPDT switch;
a first OR gate configured to logically OR the inverted EN input and the Q output of the second retriggerable monoshot, wherein an output of the first OR gate drives the reset input of the first retriggerable monoshot;
a second OR gate configured to logically OR the inverted EN input and the Q output of the first retriggerable monoshot, wherein an output of the second OR gate drives the reset input of the second retriggerable monoshot;
a third AND gate configured to logically AND the nQ output of the first retriggerable monoshot, the nQ output of the second retriggerable monoshot, and the EN input, wherein an output of the third AND gate drives the CTRL input of the third SPDT switch; and
a fourth AND gate configured to logically AND the nQ output of the first retriggerable monoshot, the nQ output of the second retriggerable monoshot, and the EN input, wherein an output of the fourth AND gate drives the CTRL input of the fourth SPDT switch.
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