US 11,989,148 B2
Data bridge for interfacing source synchronous datapaths with unknown clock phases
Ankur Bal, Greater Noida (IN); and Rupesh Singh, Ghaziabad (IN)
Assigned to STMicroelectronics International N.V., Geneva (CH)
Filed by STMicroelectronics International N.V., Geneva (CH)
Filed on Dec. 10, 2021, as Appl. No. 17/548,101.
Claims priority of provisional application 63/132,297, filed on Dec. 30, 2020.
Prior Publication US 2022/0206987 A1, Jun. 30, 2022
Int. Cl. G06F 13/42 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); H03K 3/037 (2006.01)
CPC G06F 13/42 (2013.01) [G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 3/037 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A method, comprising:
generating a first clock signal with a first subsystem of an integrated circuit;
generating a second clock signal with a second subsystem of the integrated circuit;
determining a phase difference between the first clock signal and the second clock signal; and
selecting an edge of the second clock signal based on the phase difference;
controlling transmission of data from the first subsystem to the second subsystem with the selected edge of the second clock signal;
generating, with the first subsystem, a first phase signal having a same frequency as the first clock signal and a first selected phase difference relative to the first clock signal; and
generating, with the first subsystem, a second phase signal having the same frequency as the first clock signal and a second selected phase difference relative to the first clock signal.