US 11,989,144 B2
Centralized interrupt handling for chiplet processing units
HaiKun Dong, Beijing (CN); ZengRong Huang, Shanghai (CN); Ling-Ling Wang, Santa Clara, CA (US); MinHua Wu, Shanghai (CN); Jie Gao, Shanghai (CN); and RuiHong Liu, Shanghai (CN)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Jul. 30, 2021, as Appl. No. 17/389,994.
Prior Publication US 2023/0034539 A1, Feb. 2, 2023
Int. Cl. G06F 13/24 (2006.01)
CPC G06F 13/24 (2013.01) 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a master interrupt controller, in a first semiconductor die of a plurality of semiconductor dies on a substrate, comprising circuitry configured to:
receive, via a communication link, interrupts generated by at least:
a first interrupt source in the first semiconductor die; and
a second interrupt source in a second semiconductor die of the plurality of semiconductor dies;
in response to receiving a given interrupt, determine which of the first interrupt source and the second interrupt source generated the given interrupt; and
convey the given interrupt, with an indication of which source generated the given interrupt, to a processor for handling by the processor.