| CPC G06F 13/1668 (2013.01) | 18 Claims |
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1. An accelerator, comprising:
a circuit to execute instructions on a first data batch to produce a first processed data batch, a data model including the first data batch and a second data batch, the circuit including one or more cores, the circuit configured to execute the instructions on the data model using the first data batch and the second data batch;
a first tier storage including a first capacity and a first latency;
a second tier storage including a second capacity and a second latency, the second capacity larger than the first capacity, the second latency being slower than the first latency;
a bus to transfer at least one of the first data batch or the first processed data batch between the first tier storage and the second tier storage; and
a prefetcher to transfer the first data batch from the second tier storage to the first tier storage over the bus based at least in part on data placement information from a host regarding the first data batch.
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