CPC G06F 13/1668 (2013.01) [G06N 3/004 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06562 (2013.01)] | 25 Claims |
1. A memory system, comprising:
a controller die coupled to a substrate, the controller die including a buffer, the buffer including a host interface and a die stack interface, wherein the host interface includes at least one channel, and the die stack interface includes two or more sub-channels;
a stack of memory dies supported by the substrate and coupled to the two or more sub-channels, and circuitry in the controller die, configured to operate the host interface at a first data speed, and to operate the two or more sub-channels coupled to the stack of memory dies at a second data speed, slower than the first data speed;
control logic reallocating the connections for the at least one channel to at least two sub-channels; and
one or more neuromorphic layers logically coupled between one or more dies in the stack of dies and the host interface.
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