US 11,989,140 B2
Signal path biasing in a memory system
Wolfgang Anton Spirkl, Germering (DE); Thomas Hein, Munich (DE); Martin Brox, Munich (DE); Peter Mayer, Neubiberg (DE); and Michael Dieter Richter, Ottobrunn (DE)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Feb. 10, 2023, as Appl. No. 18/108,319.
Application 18/108,319 is a division of application No. 16/849,740, filed on Apr. 15, 2020, granted, now 11,609,865.
Claims priority of provisional application 62/835,264, filed on Apr. 17, 2019.
Prior Publication US 2023/0195655 A1, Jun. 22, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 13/12 (2006.01); G11C 11/22 (2006.01); G11C 11/4093 (2006.01); G11C 11/4091 (2006.01)
CPC G06F 13/12 (2013.01) [G06F 13/1668 (2013.01); G11C 11/221 (2013.01); G11C 11/2259 (2013.01); G11C 11/4093 (2013.01); G11C 11/2273 (2013.01); G11C 11/4091 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
transmitting an access command that is associated with information to be transmitted to a memory device over a signal path using a modulation scheme that includes three or more voltage levels, the three or more voltage levels comprising a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level;
biasing, based at least in part on the access command, the signal path to a fourth voltage level between the first voltage level and the third voltage level; and
transmitting, over the signal path after biasing the signal path to the fourth voltage level, a signal modulated using the modulation scheme to include the information.