US 11,989,137 B2
Logging cache line lifetime hints when recording bit-accurate trace
Jordi Mola, Bellevue, WA (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Appl. No. 18/548,320
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
PCT Filed Mar. 21, 2022, PCT No. PCT/US2022/021099
§ 371(c)(1), (2) Date Aug. 29, 2023,
PCT Pub. No. WO2022/212098, PCT Pub. Date Oct. 6, 2022.
Claims priority of application No. 102722 (LU), filed on Mar. 31, 2021.
Prior Publication US 2024/0095187 A1, Mar. 21, 2024
Int. Cl. G06F 12/128 (2016.01); G06F 12/0895 (2016.01)
CPC G06F 12/128 (2013.01) [G06F 12/0895 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A microprocessor that records an execution trace, comprising:
a processing unit;
a memory cache; and
control logic that configures the microprocessor to at least:
based on executing a first instruction at the processing unit, detect occurrence of a first cache event that initiates a lifetime of a cache line within the memory cache;
based on detecting the first cache event, initiate logging, into the execution trace, first trace information indicating a beginning of the lifetime of the cache line within the memory cache;
subsequent to initiating logging of the first trace information, and based on executing a second instruction at the processing unit, detect occurrence of a second cache event that ends the lifetime of the cache line within the memory cache; and
based on detecting the second cache event, initiate logging, into the execution trace, second trace information indicating an ending of the lifetime of the cache line within the memory cache.