US 11,989,136 B2
Methods and systems for translating virtual addresses in a virtual memory based system
Mohit Karve, Austin, TX (US); and Brian W. Thompto, Austin, TX (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Sep. 23, 2021, as Appl. No. 17/483,136.
Application 17/483,136 is a continuation of application No. 16/701,230, filed on Dec. 3, 2019, granted, now 11,163,695.
Prior Publication US 2022/0012183 A1, Jan. 13, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/1036 (2016.01); G06F 12/0882 (2016.01); G06F 12/1009 (2016.01); G06F 13/16 (2006.01)
CPC G06F 12/1036 (2013.01) [G06F 12/0882 (2013.01); G06F 12/1009 (2013.01); G06F 13/1668 (2013.01); G06F 2212/7201 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of translating in an electronic memory system a virtual address to a second address, wherein the electronic memory system is remote from and communicates with a processor over a bus, and the electronic memory system contains a memory controller and one or more memory devices, the method comprising:
receiving, by the memory controller, a page directory base together with at least a portion of the virtual address;
determining, by the memory controller, a first level memory offset from the at least a portion of the virtual address;
obtaining, by the memory controller from the one or more memory devices, a memory line containing an address of the first level page directory table;
extracting, by the memory controller, from the memory line containing the address of the first level page directory table, the address of the first level page directory table using the page directory base and the first level memory offset;
transmitting, by the memory controller, the memory line containing the address of the first level page directory table over the bus from the memory controller to the processor;
determining, by the memory controller, a second level memory offset from the at least a portion of the virtual address; and
obtaining, by the memory controller from the one or more memory devices, a second level page directory table using the first level page directory table and the second level memory offset;
obtaining, by the memory controller, a memory line from the one or more memory devices that contains the address of the page table entry (PTE); and
extracting, by the memory controller, from the memory line containing the address of the PTE, the PTE, wherein the PTE contains the translation of the virtual address to the second address.