CPC G06F 12/10 (2013.01) [G06F 3/0622 (2013.01); G06F 3/0637 (2013.01); G06F 3/0673 (2013.01)] | 20 Claims |
1. An apparatus comprising:
translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses;
permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and,
access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address;
the access circuitry being configured to selectively allow access by the translation circuitry to a translation information address without the permission circuitry having completed the operation to detect permission information to indicate whether memory access is permitted to that translation information address.
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