US 11,989,133 B2
Logical-to-physical mapping compression techniques
Xing Wang, Shanghai (CN); Liping Xu, Shanghai (CN); Xu Zhang, Shanghai (CN); and Zhen Gu, Shanghai (CN)
Assigned to Micron Technology, Inc., Boise, ID (US)
Appl. No. 17/637,429
Filed by Micron Technology, Inc., Boise, ID (US)
PCT Filed Mar. 16, 2021, PCT No. PCT/CN2021/081018
§ 371(c)(1), (2) Date Feb. 22, 2022,
PCT Pub. No. WO2022/193120, PCT Pub. Date Sep. 22, 2022.
Prior Publication US 2023/0350808 A1, Nov. 2, 2023
Int. Cl. G06F 12/10 (2016.01)
CPC G06F 12/10 (2013.01) 25 Claims
OG exemplary drawing
 
1. A memory system, comprising:
one or more memory devices; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
receive a read command comprising a logical block address;
read, based at least in part on the logical block address, an entry of a first subset of a mapping that defines a relationship between the logical block address and a physical address, the entry comprising a flag that indicates whether the entry is associated with a second subset of the mapping or is associated with a starting physical address of a set of physical addresses associated with the read command;
read data associated with the read command starting at the physical address based at least in part on the flag indicating that the entry is associated with the starting physical address; and
transmit the data to a host system based at least in part on reading the data.