US 11,989,132 B2
Early cache querying
Yasuo Ishii, Austin, TX (US); Jungsoo Kim, Sawston (GB); James David Dundas, Austin, TX (US); and Abhishek Raja, Austin, TX (US)
Assigned to Arm Limited, Cambridge (GB)
Filed by Arm Limited, Cambridge (GB)
Filed on Jul. 14, 2022, as Appl. No. 17/864,625.
Prior Publication US 2024/0020237 A1, Jan. 18, 2024
Int. Cl. G06F 12/0897 (2016.01)
CPC G06F 12/0897 (2013.01) [G06F 2212/60 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A data processing apparatus comprising:
receive circuitry configured to receive a result signal from one of a lower level cache and a higher level cache in respect of a first instruction block, wherein the lower level cache and the higher level cache are arranged hierarchically; and
transmit circuitry configured to transmit a query to the higher level cache for a subsequent instruction block, different from the first instruction block within a time limit; and
the time limit is dependent on an origin of the result signal so that the time limit is smaller when the result signal comprising the requested data originates from the higher level cache than when the result signal comprising the requested data originates from the lower level cache.