US 11,989,131 B2
Storage array invalidation maintenance
Sreevathsa Ramachandra, Austin, TX (US); Christopher L Colletti, Austin, TX (US); and David E. Kroesche, Austin, TX (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 20, 2023, as Appl. No. 18/171,565.
Application 18/171,565 is a continuation of application No. 17/008,491, filed on Aug. 31, 2020, granted, now 11,586,551.
Prior Publication US 2023/0305965 A1, Sep. 28, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/0891 (2016.01); G06F 12/0875 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0891 (2013.01) [G06F 12/0875 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/683 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a processor core having a translation lookaside buffer (TLB), wherein the processor core is configured to retain translations cached in the TLB during a time that the processor core is in a powered-off state;
cache circuitry configured to send invalidation requests to the processor core; and
power management circuitry coupled to the processor core and the cache circuitry, wherein the power management circuitry is configured to:
communicate with the cache circuitry to block invalidation requests associated with the TLB of the processor core from reaching the processor core;
receive, from the cache circuitry and while the processor core is in the powered-off state, a set of notifications about a first set of invalidation requests directed to the processor core to invalidate a set of entries of the TLB;
store first invalidation information indicative of the first set of invalidation requests; and
prior to completion of a transition of the processor core to a run state after powering up, invalidate the set of entries of the TLB based on the first invalidation information.