| CPC G06F 11/3495 (2013.01) [G06F 9/3802 (2013.01); G06F 11/302 (2013.01)] | 22 Claims |
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1. A processor supervisory unit configured to monitor program flow executed by a processor, at a data bus configured to connect the processor to a memory, the processor supervisory unit being arranged to store a set of values representing locations to which the program flow is expected to return after jumps in the program flow, the processor supervisory unit being configured to:
monitor, at the data bus, the program flow for a jump in the program flow, the monitor of the program flow comprising identification of a location in the memory from which the processor requests an instruction, identification of content of the instruction passing to the processor from the memory, direct report to the processor supervisory unit when the processor has executed the instruction, or any combination thereof;
detect the jump in the monitored program flow;
when in a first mode, on the detection of the jump in the monitored program flow, store a location value representing a location to which the program flow is expected to return from the jump; and
when in a second mode, on the detection of the jump in the monitored program flow, increment a counter associated with a location value representing a location to which the program flow is expected to return from the jump,
wherein the processor supervisory unit is configured to store no more than a predetermined number of location values simultaneously by operating in the first mode,
wherein the processor supervisory unit has access to a plurality of stores, each configured to store a respective location value, and there is a counter associated with each of the stores, and
wherein the processor supervisory unit is configured to, when two successive stores of the plurality of stores store a same location value, treat bits representing counters associated with the location values as collectively representing a value in binary form.
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